In the manufacture of semiconductor device products, in order to detect defective semiconductor elements early so that manufacturing costs are reduced and productivity is improved, a function test is performed in which the semiconductor elements are connected to a tester and circuits are driven.
In such a function test, in order to temporarily provide wiring from the tester to electrode pads disposed on semiconductor elements, a probe card, in which probe needles are arranged in advance so as to correspond to the arrangement of the electrode pads of the semiconductor elements to be tested, is used as a card for testing semiconductor elements. Specifically, the examination of electrical characteristics of the semiconductor elements to be tested (i.e., probing test) is conducted by a method in which the probe needles of the probe card are brought into contact with the electrodes pads of the semiconductor elements to be tested using a driving device referred to as a prober.
Subsequently, the electrode pads of the semiconductor elements which have been determined to be non-defective in such a probing test are connected to inner leads or electrode terminals of a wiring substrate on which the semiconductor elements are to be mounted, using bonding wires made up of gold (Au) or the like. Namely, wire bonding is performed.
With regard to such a technique, Japanese National Publication of International Patent Application No. 2005-522019 discloses a structure in which a planarized combination of copper and silicon oxide features is provided in a bond pad region to form bond pads, and the silicon oxide features are etched back to provide a plurality of recesses in the copper in the bond pad region.
Furthermore, Japanese National Publication of International Patent Application No. 2006-502561 discloses a structure, in which beneath a pad metal, at least upper two metal layers contain at least two adjacent conductor tracks.
Furthermore, Japanese Laid-open Patent Publication No. 2005-251832 discloses a structure in which an interlayer insulation film underlying a pad surface layer is selectively left and when aluminum which forms an electrode is vapor-deposited thereon, selectively left portions rise or sink to form a recognizable pattern artificially on the surface of the electrode pad.
Furthermore, Japanese Laid-open Patent Publication No. 2008-098225 discloses a structure including a probe contact region which has a lower layer including wide slit vias and the surface of which is depressed, and a bonding region which has a lower layer including narrow slit vias, thus allowing the probe contact region and the bonding region to be clearly distinguished.
However, in the example illustrated in FIGS. 3A and 3B, because of limitations in the process of manufacturing semiconductor elements, such as the accuracy of photomasks used for exposing circuit patterns, a bonding region 13a and a test region 13b are disposed with a predetermined distance therebetween. Consequently, in the example illustrated in FIGS. 3A and 3B, it is not possible to decrease the overall length of the electrode pad, thus increasing the size of the semiconductor elements, which makes it difficult to reduce the manufacturing costs of semiconductor devices.
Furthermore, the bonding pad structure described in Japanese Laid-open Patent Publication No. 2005-251832 is a two-layered metal structure including a wiring metal layer and an uppermost metal layer disposed on the wiring metal layer. Usually, a wiring portion having a different potential is provided below the pad structure.
In such a structure, when stress is applied onto the uppermost metal layer during a probing test or a wire bonding process, although the uppermost metal layer and the wiring metal layer change shape, cracks may occur in the interlayer insulation film and the insulation film between wires located below the wiring metal layer. If such cracks extend to the wiring portion, short-circuiting may occur. In order to prevent this problem, it is necessary to form a metal layer between the wiring metal layer and the interlayer insulation film. However, formation of the metal layer increases the number of manufacturing steps, resulting in a difficulty in reducing the manufacturing costs.
Furthermore, in the structure described in Japanese Laid-open Patent Publication No. 2008-098225, the wide slit vias and narrow slit vias in which a metal, such as tungsten (W) or copper (Cu), is embedded, and an insulating film are disposed directly under the banding pad. Consequently, as in the structure described in Japanese Laid-open Patent Publication No. 2005-251832, when stress is applied onto the bonding pad, cracks may occur in the insulating film, and the cracks may extend to the wiring portion, resulting in the occurrence of short-circuiting.
Under these circumstances, it is desired to realize a technique which makes it possible to easily check whether or not a needle mark extends to a bonding region during a probing test without increasing the size of semiconductor elements.